In communication networks, high-speed digital receivers use Analog-to-Digital Converters (ADCs) to process received signal digitally. Converting a received signal into a digital form via an ADC allows a receiver to employ complex equalization logic. Usually, longer equalization is needed for higher signaling constellations and tougher channels. Thus, fast yet energy efficient, ADCs are needed in high-speed digital receivers. A typical high-speed ADC resolution is between 5 to 8 bits.
ADCs with more than 6-bit precision running at several GHz are almost impossible to build as a single-channel ADC. Therefore, typically, a number of slower ADCs are interleaved to overcome the speed limitation of a single-channel ADC. A suitable sub-ADC should provide a high speed-per-area ratio to reduce the total area of a time-interleaved ADC and an optimized speed-per-power ratio to keep the overall power consumption low. Successive-approximation-register (SAR) ADCs exhibit superior energy efficiency for medium-resolution applications.
High-speed operation can be achieved by converting each sample with two alternate comparators clocked asynchronously. The use of alternate comparators can improve the ADC speed by about 20% without consuming additional power. An ADC offset is a random additive error typically stemming from the comparator direct current (DC) offset. In a single-channel ADC, a DC offset creates a DC tone that can be easily corrected and is often ignored in many communication applications. The impact of the DC offset is much more detrimental in time-interleaved ADCs. In practical implementations, the interleaved channels can have different DC offsets, which need to be corrected through DC offset calibration processes.
FIG. 1 illustrates the configuration of a time-interleaved ADC 100 with the calibration logic 130 for calibrating DC offsets in accordance with the prior art. The ADC 100 includes two comparators 121 and 122 coupled to the track-and-hold circuit (T/H) 111 and a reference buffer 112 storing reference voltages for all the bits. The comparators 121 and 122 operate in an alternating fashion to generate respective bits of a digital output.
During operation, the input signal 101 is fed to the T/H 111, which outputs sampled signals. Each comparator compares a sampled signal with a reference voltage of a particular bit and outputs the decision signal as the digital value of a corresponding bit. More specifically, a decision 1 is output by the comparator 1 121 while the comparator 2 122 is in a reset mode. When the comparator 1 121 finishes its decision, it goes into the reset mode with minimal delay, while the comparator 2 122 is activated to make the decision 2. This provides the comparator 1 much more time for reset and thus eliminates the reset time from the critical path.
The analog calibration logic 130 utilizes a conventional analog calibration scheme to calibrate the DC offsets of the comparators 121 and 122, which demands undesirable complex analog circuit design and high power consumption. Also, the conventional calibration techniques are performed in the foreground (or “offline”), which require an interruption of the operation of the ADC. Specifically, during the time windows dedicated for calibration, the comparators stop receiving sampled signals for conversion and instead receive calibration signals generated from the calibration logic. The extra calibration time inevitably delays signal processing at the ADC and the high speed digital receiver.